1. Field of the Invention
The present invention relates to a semiconductor memory device, more particularly to the structure of charge traps in a semiconductor nonvolatile memory device.
2. Description of the Related Art
Semiconductor nonvolatile memory devices having charge traps with a silicon/oxide/nitride/oxide/silicon (SONOS) structure are known (see, for example, JP 9-64205, JP 2002-184873, and JP 2003-347543; ‘JP’ denotes a Japanese patent application publication). A conventional semiconductor nonvolatile memory cell of the SONOS type (a SONOS memory cell) will be described with reference to FIG. 1, which shows a schematic sectional view of the memory cell, and FIG. 2, which is an energy level diagram.
Referring to FIG. 1, the SONOS memory cell is formed on the surface of a silicon substrate 120, in an active area 122 isolated from other active areas by an isolation region (not shown) such as a silicon oxide film formed by local oxidation of silicon (LOCOS) or shallow trench isolation (STI). The SONOS memory cell includes a tunnel oxide film 141, a charge trapping film 142, and a blocking oxide film 147, formed in this sequence one atop another.
In one exemplary device, the tunnel oxide film 141 is formed by thermal oxidation of the surface of the silicon substrate 120 and is seven nanometers (7 nm) thick. The charge trapping film 142 and blocking oxide film 147 are formed by low-pressure chemical vapor deposition (LP-CVD) and are 6 nm and 9 nm thick, respectively. For the charge trapping film 142, the deposition temperature is 755° C., the reaction gases are ammonia (NH3) and dichlorosilane (DCS: SiH2Cl2) with respective flow rates of 1000 sccm and 100 sccm, and the deposition pressure is 33.3 Pascals (33.3 Pa, equivalent to 0.25 Torr), where the unit sccm (standard cubic centimeters per minute) represents the gas flow rate converted to a temperature of 0° C. and a pressure of 1 atmosphere (1013 hPa). Under these conditions, the charge trapping film 142 becomes stoichiometric. Specifically, the charge trapping film 142 has the formula SixNy, where x and y have values of substantially 3 and 4, respectively, resulting in an x/y ratio of substantially 0.75.
The SONOS memory cell also includes a control electrode, more specifically a gate electrode 134 having a polycide structure including a polysilicon film 135 and a tungsten silicide film 136, each approximately 100 nm thick, stacked atop the blocking oxide film 147. The polysilicon film 135 is formed by, for example, chemical vapor deposition (CVD) and is doped with phosphorous (P) at a concentration of about 3×1020 carriers/cm3. The tungsten silicide film 136 is sputtered onto the polysilicon film 135.
Diffusion regions 124a, 124b are also formed in the surface of the silicon substrate 120 on mutually opposite sides of the gate electrode 134 to function as source and drain regions. The diffusion regions 124a, 124b are doped with arsenic (As) at a dose of at least 1×1015 carriers/cm2, after which activation annealing is carried out at a temperature of about 1000° C.
The silicon substrate 120 and gate electrode 134 are protected by an interlayer dielectric film 150 of borophosphosilicate glass (BPSG), which is formed with a thickness of about 1000 nm and then planarized by chemical mechanical polishing (CMP). The interlayer dielectric film 150 includes tungsten plugs 155 that electrically connect the diffusion regions 124a, 124b and the gate electrode 134 to aluminum interconnecting lines 160 formed on the interlayer dielectric film 150.
A SONOS memory cell having the above structure stores information in the form of charge, for example, electrons, trapped in the charge trapping film 142. The charge trapping film 142 can trap electrons locally, so the charge can be stored independently on the source and drain sides of the charge trapping film 142 by generating hot carriers in either the source or drain side of the channel formed below the gate electrode 134 in the silicon substrate 120. That is, a SONOS memory can store two bits information per memory cell.
The trapping mechanism is illustrated by the energy level diagram in FIG. 2, which shows the 1.1-electron volt (1.1-eV) band gap of the silicon substrate 120, the 9-eV band gap of the tunnel oxide film 141, the 5-eV band gap of the stoichiometric charge trapping film 142, the charge trapping level ‘a’ in the forbidden band of the charge trapping film 142, the band gaps of the blocking oxide film 147 and polysilicon film 135, and the Fermi energy level Ef. The band gap is the gap between the conduction-band and the valence band. The upper boundary of the band gap is the minimum energy level of the conduction band. The upper boundary of the band gap of the charge trapping film 142 is about 1 eV below the upper boundaries of the band gaps of the tunnel oxide film 141 and blocking oxide film 147. An electron injected into the charge trapping film 142 by tunneling is accordingly confined to the charge trapping film 142 by potential energy barriers with a height of approximately 1 eV, and is likely to become trapped at level ‘a’ before it can escape.
Since the charge trapping level in the charge trapping film 142 is only about 1 eV below the upper boundary level of the band gap, however, and since the activation energy needed to inject an electron into the charge trapping film 142 is also about 1 eV, the electron trapping efficiency is not high. The charge retention characteristics of the charge trapping film 142 are also less than adequate.
A charge trapping film structure with improved charge retention characteristics and a method of manufacturing the structure are disclosed in JP 2002-184873 and JP 2003-347543. This structure will be described with reference to the schematic sectional view in FIG. 3 and the energy level diagram in FIG. 4, omitting descriptions of elements that appeared in FIG. 1.
The charge trapping film 143 in FIG. 3 has a dual-layer structure including a stoichiometric first silicon nitride film 144 and a silicon-rich second silicon nitride film 145. JP 9-64205 describes a method of forming such a charge trapping film: a stoichiometric silicon nitride film is deposited and then silicon ions are implanted into the surface of the silicon nitride film.
As shown in FIG. 4, the silicon-rich second silicon nitride film 145 has a narrower band gap than the stoichiometric first silicon nitride film 144, and a deeper charge trapping level (depth >1 eV) than the stoichiometric charge trapping film 142 in FIG. 1. Electrons injected into the charge trapping film 143 easily reach the second silicon nitride film 145, but once trapped at level ‘a’, they are confined by a high potential energy barrier between the second silicon nitride film 145 and the blocking oxide film 147, while the increased distance of the charge trapping site (‘a’) from the silicon substrate 120 reduces charge leakage into the silicon substrate 120 through the tunnel oxide film 141. Charge retention characteristics are accordingly improved.
Charge-trap semiconductor memory devices are not limited to the SONOS memory described above; there is also a sidewall type of semiconductor nonvolatile memory (referred to below simply as a sidewall memory) disclosed in, for example, JP 2005-64295. An exemplary conventional sidewall memory will be described with reference the schematic sectional view in FIG. 5.
A unit cell 210 (referred to below as a memory cell) in a sidewall memory includes a metal-oxide-semiconductor field-effect transistor (MOSFET) formed on a silicon substrate 220. The MOSFET includes a gate electrode 234, first and second diffusion regions 224a, 224b, and first and second variable resistance regions 222a, 222b. A gate electrode 234 is formed on a gate oxide film 232 disposed on the silicon substrate 220. The gate electrode 234 may have a polycide structure including a polysilicon film 235 underlying a tungsten silicide film 236, as shown.
The first and second diffusion regions 224a, 224b are formed by diffusing, for example, an n-type impurity into the regions located on mutually opposite sides of the gate electrode 234. These regions function interchangeably as the source and drain of the MOSFET.
The first and second variable resistance regions 222a, 222b are disposed between the first and second diffusion regions 224a, 224b and the gate electrode 234, and have the same conductivity type as the first and second diffusion regions 224a, 224b. In this example, an n-type impurity is diffused into the first and second variable resistance regions 222a, 222b, but at a lower concentration than in the first and second diffusion regions 224a, 224b. 
This semiconductor nonvolatile memory has a first charge trap 240a on the first variable resistance region 222a and a second charge trap 240b on the second variable resistance region 222b. The first and second charge traps 240a, 240b both have a multi-layer charge-trapping structure comprising a tunnel oxide film 241, a silicon nitride charge trapping film 243 overlying the tunnel oxide film 241, and a top oxide film 247 overlying the charge trapping film 243, forming an oxide-nitride-oxide (ONO) dielectric stack.
To inject electrons into the first charge trap 240a, for example, a positive voltage is applied to the gate electrode 234 and the first diffusion region 224a, which functions as the drain, and the second diffusion region 224b (functioning as the source) and substrate 220 are connected to ground. Under these conditions, electrons flow through a channel that forms below the gate electrode 234 between the source and drain. As they pass through the first variable resistance region 222a, the electrons are brought into high energy states by the strong electric field emanating from the drain and become so-called hot carriers. These hot electrons are pulled into the first charge trap 240a by the electric field emanating from the gate electrode 234, and become trapped in the charge trapping film 243.
The state with injected electrons trapped in the charge trapping film 243 is defined as representing the data ‘1’ and is referred to as the programmed state, whereas the state without trapped electrons is defined as representing the data ‘0’ and is referred to as the erased state.
When electrons are trapped in the first charge trap 240a, for example, the electric field from the trapped electrons expels electrons from the surface of the first variable resistance region 222a, reducing the number of carriers (electrons) available to conduct current and thus increasing the electrical resistance of the first variable resistance region 222a. If the adjacent first diffusion region 224a is connected to ground and the second diffusion region 224b and the gate electrode 234 are biased at a positive potential, thereby reversing the source and drain roles, an electron current flows to the drain (which is now the second diffusion region 224b), but at a reduced rate because of the increased resistance of the first variable resistance region 222a. If no electrons are trapped in the first charge trap 240a, the resistance value of the first variable resistance region 222a is not increased, and the normal drain current is obtained. The stored data value (‘1’ or ‘0’) is read by sensing the drain current.
The charge trapping film described in JP 2002-184873 and JP 2003-347543, having a multi-layer structure including a stoichiometric silicon nitride film and a silicon-rich silicon nitride film formed in sequence on the tunnel oxide film, is regarded as an adequately effective SONOS semiconductor memory structure. Direct application of this charge trapping film to the conventional sidewall memory shown in FIG. 5, however, is thought to be inappropriate. The reason for this will be described with reference to FIGS. 5 to 8.
FIGS. 6 to 8 illustrate the charge trapping location dependency of the drain current of the sidewall nonvolatile memory cell in FIG. 5 when the first charge trap 240a is programmed and the second charge trap 240b is erased. FIGS. 6 and 7 are enlarged sectional views of parts of the first charge trap 240a and first variable resistance region 222a. In FIG. 6, charge is trapped at a location X near the interface 241a between the tunnel oxide film 241 and the charge trapping film 243; in FIG. 7, charge is trapped at a location Y at some distance from this interface 241a. 
FIG. 8 is a graph obtained by simulating the drain currents when the programmed and erased data are read. The horizontal axis represents gate voltage Vgate in volts and the vertical axis represents drain current Idrain in amperes. Drain currents are shown as positive when the first diffusion region 224a is grounded and the second diffusion region 224b is biased at a positive voltage, and negative when the second diffusion region 224b is grounded and the first diffusion region 224a is biased at a positive voltage.
In the example in FIG. 8, since the first charge trap 240a has been programmed by injecting electrons and the second charge trap 240b is in the erased state, the drain currents IX, IY for reading the programmed data are obtained when the first diffusion region 224a is grounded and the second diffusion region 224b biased at a positive potential. The magnitude of these currents indicates whether charge is trapped in the first charge trap 240a or not.
The drain currents IIX, IIY for reading the erased data are obtained by reversing the biasing of the first and second diffusion regions 224a, 224b so that the second diffusion region 224b is at the ground potential and the first diffusion region 224a is at a positive potential. The magnitude of these currents indicates whether charge is trapped in the second charge trap 240b or not.
Curves IX and IIX in FIG. 8 represent the currents flowing when charge is trapped near the interface 241a in the first charge trap 240a as shown in FIG. 6. Curves IY and IIY represent the currents flowing when charge is trapped in the first charge trap 240a at a position distant from the interface 241a as shown in FIG. 7.
These currents were simulated under the assumptions that the thickness of the tunnel oxide film 241 is 65 nm and the distance from the interface 241a to location Y in FIG. 7 is 40 nm.
When charge is trapped at location X near the interface 241a between the tunnel oxide film 241 and the charge trapping film 243, the drain current curve IX for the programmed state differs greatly from the drain current curve IIX for the erased state. The programmed and erased states can accordingly be easily distinguished.
In contrast, when charge is trapped at location Y, distant from the interface 241a between the tunnel oxide film 241 and the charge trapping film 243, the drain current curve IY for the programmed state is almost identical to the drain current curve IIY for the erased state, although their signs are opposite in FIG. 8. The programmed and erased states are therefore difficult to distinguish; the memory cell cannot be expected to function properly.
A charge trapping film with the structure disclosed in JP 2002-184873 and JP 2003-347543 (FIG. 3) traps electrons at positions comparatively distant from the silicon substrate, and thus distant from the interface between the charge trapping film and the tunnel oxide film. Therefore, this structure is not appropriate for a charge trapping film used in a sidewall memory.